1. Field of the Invention
The present invention relates to a protection circuit which protects the circuit elements of a semiconductor integrated circuit device, and more particularly to a protection circuit which prevents the circuit elements formed in the vicinity of an external terminal from being electrostatically destroyed even if a voltage arising from electrostatic discharge (hereinafter referred to as ESD) is abruptly applied to the external terminal.
2. Description of the Related Art
If the input pin of the semiconductor device is applied with a high voltage arising from ESD (e.g., the discharge of static electricity from the human body, etc.), it may happen that internal elements of a semiconductor device will be electrostatically destroyed. In order to prevent such electrostatic destruction, the semiconductor device is provided with a protection circuit located between the signal input pad of a semiconductor integrated circuit and the input circuit of internal elements.
The protection circuit is obtained by parasitically producing a bipolar transistor in the semiconductor device. An example of a conventional parasitic bipolar transistor of this type will be described. Let it be assumed that a signal input pad is connected to the input terminal of the input buffer of an internal circuit, by way of a first resistor for protection (e.g., a diffusion layer formed in the surface region of a semiconductor substrate) and a second resistor which is parasitically produced by provision of wiring layers on the semiconductor substrate. In this case, a parasitic bipolar transistor is produced such that it electrically connects the first and second resistors to either a power supply terminal or a grounded terminal.
In this conventional parasitic bipolar transistor, the substrate of the semiconductor integrated circuit functions as a base, a first diffusion region connected to the protective resistor functions as a collector, and a second diffusion region which is formed in the major-surface region of the substrate and is connected to either the power supply terminal or the grounded terminal functions as an emitter. With this structure, even if positive static charge is abruptly applied to the signal input pad, it is guided to either the power supply terminal VCC or the grounded terminal VSS through the parasitic bipolar transistor.
However, with the recent trend toward both high integration of semiconductor devices and use of smaller-size chips, it has become difficult to ensure a sufficiently large pattern area for the above parasitic bipolar transistor. In addition, since the resistance of the power supply lines provided inside a chip tends to increase in accordance with a decrease in the size of the chip, it may happen that the above-mentioned bipolar transistor will fail to reliably guide an excessive current to the outside of the semiconductor device. In particular, if the excessive current is produced by ESD and is therefore large in amount, it cannot be guided to the outside of the semiconductor device. As a result, the gates of the circuit elements formed on the neighboring substrate surface portion and the junctions inside the substrate are likely to be destroyed.